This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-306798, filed Oct. 28, 1999; and No. 2000-284708, filed Sep. 20, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a variable gain circuit which is used for a portable radio transceiver or the like to linearly change the gain displayed in decibels (dB) in accordance with a gain control signal.
Recently, mobile communication facilities typified by portable telephones have been vigorously developed. These communication facilities are carried by users and mounted on automobiles and the like when they are used, and hence required to be reduced in size and weight. It is therefore strongly desired that the components of such a radio device be implemented in monolithic IC (Integrated Circuit) form suited for reductions in size and weight rather than being implemented in hybrid form having many components connected to each other as in the prior art.
There have been demands for a reduction in the cost of radio devices as well as a reduction in the size of components. The IC technology is also effective for a reduction in the cost of radio devices.
In addition, transmission power control is indispensable to CDMA (Code Division Multiple Access) radio transceivers that have been increasingly developed in recent years. Under certain circumstances, therefore, a transmission IF (Intermediate Frequency) variable gain circuit is required to perform signal level control on 70 dB or higher. In general, to perform such high-level gain control, the gain displayed in decibels is required to be linearly adjusted in accordance with a gain control signal. This operation is required to facilitate gain control.
FIG. 16 is a circuit diagram of a conventional variable gain circuit using bipolar transistors. This variable gain circuit is comprised of a variable gain amplifier 1 and a control signal compensation circuit 2. Bipolar transistors Q1 and Q2 constitute a differential pair. An IF signal (input current Isig) is input to the common emitter terminal. An output current Ia is extracted from the collector terminal of the bipolar transistor Q1. To generate the output current Ia from an input current Isig, a gain control signal Vz1 is input between the base terminals of the bipolar transistors Q1 and Q2. Note that the arrows in FIG. 16 indicate the directions of currents.
A current Isig-Ia flowing in the collector of the bipolar transistor Q2 is regarded as an unwanted current and designed to flow in a power supply (not shown) or the like. In this case, a transfer function from Isig to Ia is represented by                                           I            a                                I            sig                          =                  1                      1            +                          exp              ⁡                              (                                                      V                    z1                                                        V                    T                                                  )                                                                        (        1        )            
where VT is the thermal voltage, which is about 26 mV at room temperature.
According to equation (1), under the condition of 1 less than  less than exp(Vz1/VT), the transfer function can be approximated by Ia/Isig=1/exp(Vz1/VT). Obviously, as the gain control signal Vz1 increases, the gain (Ia/Isig) exponentially decreases.
If the above hypothesis (1 less than  less than exp(Vz1/VT)) does not hold, the relationship between the gain control signal Vz1 and the gain (Ia/Isig) deviates from an exponential relationship. That is, if the hypothesis of 1 less than  less than exp(Vz1/VT) does not hold with respect to the gain control signal Vz1, the relationship between the gain (Ia/Isig) displayed in decibels and the gain control signal Vz1 becomes nonlinear. For this reason, there is proposed a variable gain circuit whose gain (Ia/Isig) decreases exponentially with respect to an internal gain control signal Vx by using a gain control signal compensation circuit 2 comprised of the bipolar transistors Q10 and Q11, a current source Io, a voltage source VBB, and a gain control current source I1=Ioxc2x7exp(xe2x88x92bxc2x7Vx) for gain correction [see Japanese Patent Application No. 10-370290 (Jpn. Pat. Appln. KOKAI Publication No. 2000-196386) as the specification of a previous application]. When this gain control signal compensation circuit 2 is used, the gain control signal Vx and gain (Ia/Isig) are given by                                           I            a                                I            sig                          =                  exp          ⁡                      (                                          -                b                            ·                              V                x                                      )                                              (        2        )            
where b is a constant, which is 2 to 4, for example. FIG. 17A is a block diagram of a conventional variable gain circuit using bipolar transistors. FIG. 17B is a graph showing the relationship between an external gain control signal Vc supplied from the outside of the variable gain circuit and a voltage gain GAIN (Vout/Vin) (dB). Reference symbol (dB) denotes a gain displayed in decibels; ditto for the following description. In this case, the external gain control signal Vc is equal to the internal gain control signal Vx, and Isig=g1xc2x7Vin and Ia=g2xc2x7Vout, where g1 and g2 are the conductance, which is, for example, 0.1(A/V).
By using the block arrangement shown in FIG. 17A, the internal gain control signal Vx and gain (Ia/Isig) have an exponential relationship. However, this relationship holds only when bipolar transistors are used.
More specifically, if the variable gain circuit in FIG. 16 is formed by using field-effect transistors (FETs), the internal gain control signal Vx and gain (Ia/Isig) cease to have an exponential relationship. This problem will be described in detail below.
Note that the following FETs indicate n-type (n-channel) MOS transistors (MOSFETS) unless otherwise specified.
FIG. 18 shows the variable gain circuit in FIG. 16 which is formed by using MOSFETS, assuming that FETs are MOSFETS. In this case, with the use of the internal gain control signal Vx, ID1 is given by
ID1=Ioxc2x7exp(xe2x88x92bxc2x7Vx)xe2x80x83xe2x80x83(3)
where Io is the current value of a constant current source, and b is a constant. Referring to FIG. 18, ID2=Ioxe2x88x92ID1 holds. When this circuit is designed so that the current densities of the transistors M1 and M2 equal to those of the transistors M10 and M11, a current gain GMOS (=Iout1/Isig1) of a variable gain amplifier 11 is given by                               G          MOS                =                                            gm              11                                                      gm                11                            +                              gm                10                                              =                                    gm              1                                                      gm                1                            +                              gm                2                                                                        (        4        )            
where gm1, gm2, gm10 and gm11 are the transconductance of MOS transistors M1, M2, M10 and M11. Assuming that each of the transistors M10 and M11 exhibits a square characteristic which is a characteristic in a strong inversion, the relationships between currents ID10 and ID11 and gate voltages VGS10 and VGS11 are expressed as
ID10=xcex2(VGS10xe2x88x92VTH)2xe2x80x83xe2x80x83(5)
ID11=xcex2(VGS11xe2x88x92VTH)2xe2x80x83xe2x80x83(6)
where ID10 is the drain current of the transistor M10, ID11 is the drain current of the transistor M11, VGS10 is the gate-to-source voltage of the transistor M10, VGS11 is the gate-to-source voltage of the transistor M11, xcex2 is xcexcxc2x7Coxxc2x7W/(2L), xcexc is the mobility of carriers, Cox is the oxide film capacitance per unit area, W is the channel width, L is the channel length, and VTH is the threshold voltage. From equations (4), (5), and (6), GMOS is given by                               G          MOS                =                              2            ⁢                                          β                ·                                  I                  D1                                                                          2            ⁢                          (                                                                                          β                      ·                                              I                        D1                                                              +                                                  ⁢                                                      β                    ·                                          I                      D2                                                                                  )                                                          (        7        )                                          xe2x80x83                ⁢                  =                                                    I                D1                                                              I                  o                                +                                  2                  ⁢                                                                                    I                        D1                                            ·                                              I                        D2                                                                                                                                                    (        8        )                                          xe2x80x83                ⁢                  =                                                                      I                  o                                ·                                  exp                  ⁡                                      (                                                                  -                        b                                            ·                                              V                        x                                                              )                                                                                                I                  o                                +                                  2                  ⁢                                                                                    I                        D1                                            ·                                              I                        D2                                                                                                                                                    (        9        )            
According to equation (9), if ID1 greater than  greater than ID2 or ID1 less than  less than ID2, the denominator in the root in the equation (9) can be approximated by Io. Equation (9) can therefore be rewritten as:
GMOS={square root over (exp(xe2x88x92bxc2x7Vx))}xe2x80x83xe2x80x83(10)
It is obvious from equations (10) and (2) that the relationship between the gain (dB) and the internal gain control signal Vx in the case where MOSFETs are used gradually approaches a straight line with a half slope as compared with the case where bipolar transistors are used.
If ID1=ID2=Io/2, i.e., Vz1=0, since the denominator in the root in equation (9) becomes 2Io, the gain takes a value as low as 3 dB with respect to the asymptote based on the gain control signal Vx and the gain GMOS (dB) obtained in the case where MOSFETs are used. If ID1 less than  less than ID2, the current characteristic of each of the MOSFETs M1 and M11 deviates from the square characteristic and has an exponential characteristic. This characteristic is obtained when the transistor is in a weak inversion and approximated by
ID1=Axc2x7exp{c(VGSxe2x88x92VTH1)}xe2x80x83xe2x80x83(11)
where A, c, and VTH are constants, and VGS is the gate-to-source voltage of the transistor M1. At this time, gm1=cxc2x7ID1, the gain GMOS can be approximated by                               G          MOS                =                              c            ·                          I              D1                                                          c              ·                              I                D1                                      +                          2              ⁢                                                β                  ·                                      I                    D2                                                                                                          (        12        )                                          xe2x80x83                ⁢                  ~                                    c              ·                              I                o                            ·                              exp                ⁡                                  (                                                            -                      b                                        ·                                          V                      x                                                        )                                                                    2              ⁢                                                β                  ·                                      I                    o                                                                                                          (        13        )            
where cxc2x7ID1 less than  less than 2{square root over ((xcex2xc2x7ID2))} and ID2 is up to Io. From this equation, if ID1 less than  less than ID2, the same slope as that of the characteristic curve based on bipolar transistors is obtained.
Gain characteristics in consideration of the two operation regions of MOSFETs described above are shown in FIG. 1A. As is obvious from FIG. 1A as well, when MOSFETs are used, the gain (dB) does not change linearly with respect to the external gain control signal Vc (=Vx). In controlling the gain of a radio transceiver, for the sake of easy control, it is required that the relationship between the gain (dB) displayed in decibels and the external gain control signal Vc can be linearly approximated. According to the characteristics of a variable gain circuit using MOSFETs, in particular, the relationship between the gain (dB) and the external gain control signal Vx cannot be linearly approximated in the condition that VGA""s gain is high. If gain control is performed within the range in which linear approximation can be performed, the gain control range narrows. Accordingly, the number of variable gain amplifiers must be increased, resulting in an increase in current consumption. Furthermore, in general, an amplifier has low-noise characteristics at high gain, and hence the noise characteristics deteriorate.
It is an object of the present invention to provide a variable gain circuit which uses field-effect transistors and can linearly adjust the gain displayed in decibels in accordance with an externally supplied control signal.
According to a first aspect of the invention, there is provided a variable gain circuit comprising a variable gain amplifier which receives an input signal, outputs an amplified signal, and includes a first field-effect transistor, a gain control signal compensation circuit which outputs a gain control signal for controlling a gain of the variable gain amplifier and includes a second field-effect transistor, and a gain deviation correction circuit which corrects a gain deviation based on the amplified signal of the variable gain amplifier and the gain control signal of the gain control signal compensation circuit.
According to a second aspect of the invention, there is provided a variable gain circuit comprising a first variable gain amplifier which receives an input signal, outputs an amplified signal, and includes a first field-effect transistor, a second variable gain amplifier which receives the amplified signal, outputs an amplified output signal, and includes a second field-effect transistor, a first gain control signal compensation circuit which outputs a first gain control signal for controlling a gain of the first variable gain amplifier and includes a third field-effect transistor, a second gain control signal compensation circuit which outputs a second control signal for controlling a gain of the second variable gain amplifier, and a third gain control signal compensation circuit which receives an externally supplied external gain control signal, converts the external gain control signal into an internal gain control signal, and outputs the internal gain control signal to the first and second gain control signal compensation circuits.
According to a third aspect of the invention, there is provided a variable gain circuit comprising a first variable gain amplifier which receives an input signal, outputs an amplified signal, and includes a first field-effect transistor, a second variable gain amplifier which receives the amplified signal, outputs an amplified output signal, and includes a second field-effect transistor, a first gain control signal compensation circuit which outputs a first gain control signal for controlling a gain of the first variable gain amplifier and includes a third field-effect transistor, a second gain control signal compensation circuit which receives the first gain control signal and outputs a second gain control signal for controlling a gain of the second variable gain amplifier, and a third gain control signal compensation circuit which receives an externally supplied external gain control signal, converts the external gain control signal into an internal gain control signal, and outputs the internal gain control signal to the first gain control signal compensation circuit.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.